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http://software.intel.com/en-us/articles/intel-performance-counter-monitor/


root@vcaruso-ubuntu-t5500:/home/vcaruso/src/IntelPerformanceCounterMonitorV1.7# ./pcm.x 1

EXEC : instructions per nominal CPU cycle
IPC : instructions per CPU cycle
FREQ : relation to nominal CPU frequency='unhalted clock ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
AFREQ : relation to nominal CPU frequency while in active state (not in power-saving C state)='unhalted clock ticks'/'invariant timer ticks while in C0-state' (includes Intel Turbo Boost)
L3MISS: L3 cache misses
L2MISS: L2 cache misses (including other core's L2 cache *hits*)
L3HIT : L3 cache hit ratio (0.00-1.00)
L2HIT : L2 cache hit ratio (0.00-1.00)
L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in some cases could be >1.0 due to a higher memory latency
L2CLK : ratio of CPU cycles lost due to missing L2 cache but still hitting L3 cache (0.00-1.00)
READ : bytes read from memory controller (in GBytes)
WRITE : bytes written to memory controller (in GBytes)
Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT | L2HIT | L3CLK | L2CLK | READ | WRITE

0 1 0.03 0.25 0.12 1.04 319 4131 0.92 0.04 0.07 0.17 N/A N/A
1 1 1.19 1.14 1.05 1.06 105 2803 0.96 0.96 0.00 0.01 N/A N/A
2 1 0.01 0.24 0.06 1.04 208 1152 0.82 0.04 0.08 0.09 N/A N/A
3 1 0.01 0.28 0.04 1.04 18 783 0.98 0.00 0.01 0.11 N/A N/A
4 0 0.03 0.37 0.07 0.48 566 2359 0.76 0.12 0.20 0.13 N/A N/A
5 0 0.12 0.55 0.22 0.76 591 4982 0.88 0.37 0.07 0.11 N/A N/A
6 0 0.01 0.32 0.03 0.48 13 753 0.98 0.00 0.01 0.12 N/A N/A
7 0 0.02 0.37 0.06 0.48 210 1666 0.87 0.08 0.09 0.16 N/A N/A
------------------------------------------------------------------------------------------------------------
SKT 0 0.02 0.43 0.04 0.56 1920 17 K 0.89 0.18 0.09 0.15 0.00 0.00
SKT 1 0.20 0.85 0.24 1.05 15 K 25 K 0.39 0.73 0.26 0.04 0.00 0.00
------------------------------------------------------------------------------------------------------------
TOTAL * 0.17 0.96 0.18 0.96 17 K 47 K 0.63 0.84 0.09 0.03 0.00 0.00

Instructions retired: 32 M ; Active cycles: 34 M ; Time (TSC): 7144 Kticks ; C0 (active,non-halted) core residency: 18.46 %

PHYSICAL CORE IPC : 0.96 => corresponds to 23.94 % utilization for cores in active state
Instructions per nominal CPU cycle: 0.17 => corresponds to 4.22 % core utilization over time interval

Intel(r) QPI data traffic estimation in bytes (data traffic coming to CPU/socket through QPI links):

QPI0 QPI1
----------------------------------------------------------------------------------------------
SKT 0 178 K 380 K
SKT 1 221 K 42 K
----------------------------------------------------------------------------------------------
Total QPI incoming data traffic: 823 K QPI data traffic/Memory controller traffic: 0.62

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